Intel plans exaFLOP/s supercomputer by 2018
Intel plans to achieve exaFLOP performance (one quintillion computer operations per second) by the end of this decade, according to Kirk Skaugen, Intel Corporation vice president and general manager of the Data Center Group.
The performance of the TOP500 #1 system is estimated to reach 100 PetaFLOP/s in 2015 and break the barrier of 1 ExaFLOP/s in 2018. By the end of the decade the fastest system on Earth is forecasted to be able to provide performance of more than 4 ExaFLOP/s, according to Intel.
Managing the explosive growth in the amount of data shared across the Internet, finding solutions to climate change, managing the growing costs of accessing resources such as oil and gas, and a multitude of other challenges require increased amounts of computing resources that only increasingly high-performing supercomputers can address, Skaugen said.
Intel’s relentless pursuit of Moore’s Law — doubling the transistor density on microprocessors roughly every 2 years to increase functionality and performance while decreasing costs — combined with an innovative, highly efficient software programming model and extreme system scalability are key ingredients for crossing the threshold of petascale computing into a new era of exascale computing, according to Intel.
With this increase in performance, though, comes a significant increase in power consumption. As an example, for today’s fastest supercomputer in China, the Tianhe-1A, to achieve exascale performance, it would require more than 1.6 GW of power – an amount large enough to supply electricity to 2 million homes – thus presenting an energy efficiency challenge.
To address this challenge, Intel and European researchers have established three European labs. One of their technical goals is to create simulation applications that begin to address the energy efficiency challenges of moving to exascale performance.
The company outlined its vision at the International Supercomputing Conference, which showcased Intel’s latest work in its Many Integrated Core (MIC) architecture.